Based FPGA Synthesis for Multi - Output

1 Communication Based FPGA Synthesis for Multi-Output Boolean Functions Christoph Scholl Paul Molitor Department of Computer Science Department of Computer Science Universit at des Saarlandes Martin-Luther Universit at Halle D 66041 Saarbr ucken, FRG D-06099 Halle (Saale), FRG Tel: ++49 681 302-2274 Tel: ++49 345 622 529 Fax: ++49 681 302-4421 Fax: ++49 345 622 514 e-mail: [email protected] e-mail: [email protected] Abstract| One of the crucial problems multi-level logic synthesis techniques for multi-output boolean functions f = (f1; : : : ; fm) : f0; 1gn ! f0; 1gm have to deal with is nding sublogic which can be shared by di erent outputs, i.e., nding boolean functions = ( 1; : : : ; h) : f0; 1gp ! f0; 1gh which can be used as common sublogic of good realizations of f1; : : : ; fm. In this paper we present an e cient robdd based implementation of this Common Decomposition Functions Problem (cdf). Formally, cdf is de ned as follows: Given m boolean functions f1; : : : ; fm : f0; 1gn ! f0; 1g, and two natural numbers p and h, nd h boolean functions 1; : : : ; h : f0; 1gp ! f0; 1g such that 81 k m there is a decomposition of fk of the form fk(x1; : : : ; xn) = g(k)( 1(x1; : : : ; xp); : : : ; h(x1; : : : ; xp); (k) h+1(x1; : : : ; xp); : : : ; (k) rk (x1; : : : ; xp); xp+1; : : : ; xn) using a minimal number rk of single-output boolean decomposition functions. Experimental results applying the method to FPGA synthesis are promising.